1. Field of the Invention
The invention relates generally to semiconductor integrated circuits and, more particularly, to a semiconductor integrated circuit operating in synchronism with an externally applied reference signal.
2. Description of the Background Art
FIG. 5 is a block diagram illustrating one example of a conventional semiconductor integrated circuit operating in synchronism with an externally applied reference signal.
The semiconductor integrated circuit of FIG. 5 comprises a plurality of sequential circuits 11, 12, 13, 14 and a plurality of combination circuits 21, 22, 23, 24. The combination circuits 21-24 are arranged between sequential circuits, respectively. Input data Din is applied to sequential circuit 11, predetermined processing related to the data is performed in sequential circuits 11-14 and combination circuits 21-24, and the result of processing is output as output data Dout from combination circuit 24 Each of sequential circuits 11-14 operates in response to an externally applied reference signal CK.
A sequential circuit is a circuit of which output state at a given time is determined by a prior input state. A combination circuit is a circuit which output state at a given time is determined by an input state at that time. One of the simplest examples of sequential circuits and combination circuits is shown in FIG. 6. A transfer gate formed by transistor is an example of a sequential circuit. A circuit structured by logic gates is an example of a combination circuit.
In the semiconductor integrated circuit of FIG. 5, the upper limit of its operation speed, that is, the upper limit of the frequency of reference signal CK is determined by the largest delay amount among delay amounts (delay time period) which combination circuits 21-24 respectively have. Assume that, for example, combination circuit 21 has a delay amount D1 of 100 ms, and combination circuits 22, 23, 24 have delay amounts D2, D3, D4 of 90 ms, respectively. In this case, the frequency of reference signal CK is determined by delay amount D1 of combination circuit 21, and therefore it is 10Hz. Thus, no matter how small delay amounts D2, D3, D4 of the other combination circuits 22, 23, 24 are, the maximum operation speed of the semiconductor integrated circuit is determined by the delay amount of combination circuit 21.
A delay amount of a sequential circuit can be assumed to be almost 0.
FIG. 7 is a block diagram illustrating another example of a conventional semiconductor integrated circuit operating in synchronism with an externally applied reference signal.
The semiconductor integrated circuit of FIG. 7 further comprises a timing signal generating circuit 2 generating two kinds of timing signal CK10, CK20 in response to an externally applied reference signal CK. Sequential circuits 11, 14 operate in response to a rise of timing signal CK10 and sequential circuits 12, 13 operate in response to a rise of timing signal CK20. The time period from the time point of operation of sequential circuit 11 to the time point of operation of sequential circuit 12 is shown as T11 and the time period from the time point of operation of sequential circuit 12 to the time point of operation of sequential circuit 13 is shown as T12. The time period from the time point of operation of sequential circuit 13 to the time point of operation of sequential circuit 14 is shown as T13.
A timing chart of externally applied reference signal CK and timing signals CK10, CK20 is shown in FIG. 8.
A period of reference signal CK is CY. Timing signals CK10, CK20 have the same period CY as that of reference signal CK. Timing signal CK20 is delayed by delay time period .alpha. with respect to timing signal CK10. The following expression is obtained, because the time period T11 from the time point of operation of sequential circuit 11 to the time point of operation of sequential circuit 12 needs to be greater than delay amount D1 of combination circuit 21. EQU T11=CY+.alpha..gtoreq.D1 (1)
The following expression is obtained, because the time period T12 from the time point of operation of sequential circuit 12 to the time point of operation of sequential circuit 13 needs to be greater than delay amount D2 of combination circuit 22. EQU T12=CY.gtoreq.D2 (2)
The following expression is obtained, because the time period from the time of operation of sequential circuit 13 to the time point of operation of sequential circuit 14 needs to be greater than delay amount D3 of combination circuit 23. EQU T13=CY-.alpha..gtoreq.D3 (3)
Assuming that, for example, D1=100 ms, D2=D3=D4 =90 ms, .alpha.=5 ms, the expression (1) can be as shown below. EQU T11=CY+5.gtoreq.100
The expression (3) can be as shown below. EQU T13=CY-5.gtoreq.90
Therefore, CY.gtoreq.95.
As a result, it is possible to set the frequency of reference signal CK at 1000/95=10.5 Hz.
Thus, it is possible to increase the operation speed of a semiconductor integrated circuit.
In a case where a plurality of combination circuits have different delay amounts in the semiconductor integrated circuit of FIG. 7, an increase in an operation speed can be achieved by employing two kinds of timing signals CK10, CK20.
However, an operation speed cannot be increased in a case where delay amounts of all combination circuits 21-24 are large. Assume, for example, that delay amounts D1-D4 of combination circuits 21-24 are all 100 ms. In this case, in order to satisfy the expression (1) and (3), for example, delay time period .alpha. needs to be 0 and one period CY needs to be 100 ms. It is, therefore, necessary to set the frequency of reference signal CK at 10 Hz.
Thus, in the semiconductor integrated circuit of FIG. 7, when delay amounts of all combination circuits are large, an increase in an operation speed cannot be achieved.